The present invention relates to semiconductor technology, and more particularly to nonvolatile memories.
FIGS. 1-8 illustrate fabrication of a conventional nonvolatile stacked-gate flash memory described in U.S. Pat. No. 6,013,551 issued Jan. 11, 2000 to J. Chen et al. Silicon oxide layer 108 (xe2x80x9ctunnel oxidexe2x80x9d) is grown on P-type silicon substrate 150. Doped polysilicon 124 is deposited over oxide 108. Polysilicon 124 will provide floating gates for memory cell transistors.
Mask 106 is formed over the structure. Polysilicon 124, oxide 108, and substrate 150 are etched through the mask openings. Trenches 910 are formed in the substrate as a result (FIG. 2).
As shown in FIG. 3, the structure is covered with dielectric which fills the trenches. More particularly, silicon oxide 90 is grown by thermal oxidation. Then silicon oxide 94 is deposited by PECVD (plasma enhanced chemical vapor deposition). Then thick silicon oxide layer 96 is deposited by SACVD (subatomspheric chemical vapor deposition).
The structure is subjected to chemical mechanical polishing (CMP). Polysilicon 124 becomes exposed during this step, as shown in FIG. 4.
As shown in FIG. 5, ONO (silicon oxide, silicon nitride, silicon oxide) layer 98 is formed on the structure. Silicon 99 is deposited on top. Then tungsten silicide 100 is deposited.
Then a mask is formed (not shown), and the layers 100, 99, 98, 124 are patterned (FIG. 6). Layer 124 provides floating gates, and layers 99, 100 provide control gates and wordlines.
Then mask 101 is formed over the structure, as shown in FIG. 8. Silicon oxide etch removes those portions of oxide layers 90, 94, 96 which are exposed by mask 101. After the etch, the mask remains in place, as dopant is implanted to form source lines 103.
Other implantation steps are performed to properly dope the source and drain regions.
Alternative memory structures and fabrication methods are desirable.
To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one of the structures and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.
Other features and advantages of the invention are described below. The invention is defined by the appended claims.